Hai Wang (王海)

中文主页（Chinese Homepage）

• Professor, University of Electronic Science and Technology of China (UESTC)
• E-mail: wanghai@uestc.edu.cn

Education

• Ph.D., University of California at Riverside, USA, 2012
• M.S., University of California at Riverside, USA, 2008
• B.S., Huazhong University of Science and Technology, China, 2007

Research Areas

• Artificial intelligence (AI) assisted integrated circuit design
• Electronic design automation of integrated systems (EDA)
• Computer design

• Short Bio
• Selected Publications
• Open Source Software
• Selected Projects

Short Bio

Hai Wang received the B.S. degree from Huazhong University of Science and Technology, China, and the M.S. and Ph.D. degrees from University of California, Riverside, in 2007, 2008, and 2012, respectively. He is currently a professor with the University of Electronic Science and Technology of China. His research interests include modeling, optimization, and artificial intelligence assisted design automation of VLSI circuits and systems.

Dr. Wang has served on the organizing committee of International Conference on Computer Design (ICCD), technical program committee of Design Automation and Test Conference in Europe (DATE), Asia and South Pacific Design Automation Conference (ASP-DAC), International Symposium on Quality Electronic Design (ISQED), and International Green and Sustainable Computing Conference (IGSC, formerly called IGCC). He also served as reviewer of many journals including IEEE Transactions on Computers (TC), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Transactions on Parallel and Distributed Systems (TPDS), and ACM Transactions on Design Automation of Electronic Systems (TODAES).

Dr. Wang was a recipient of the Best Paper Award nomination from Asia and South Pacific Design Automation Conference (ASP-DAC) in 2019, at Tokyo, Japan.

Click here for the slides which introduce our recent research advances.

Selected Publications (since 2016)

The authors with star marker * are my students.

1. H. Wang, X. Long*, and X.-X. Liu, "FastESN: Fast echo state network", IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2022. (early access, JCR Q1, IF 10.4, CCF B rank)
2. H. Wang, W. He*, Q. Yang*, X. Peng, and H. Tang, "DBP: Distributed power budgeting for many-core systems in dark silicon", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022. (early access, CCF A rank)
3. H. Wang, W. Li*, W. Qi*, D. Tang*, L. Huang, and H. Tang, "Runtime performance optimization of 3-D microprocessors in dark silicon", IEEE Transactions on Computers (TC), vol. 70, no. 10, pp. 1539-1554, October 2021. (CCF A rank)
4. H. Wang, L. Hu*, X. Guo*, Y. Nie, and H. Tang, "Compact piecewise linear model based temperature control of multi-core systems considering leakage power", IEEE Transactions on Industrial Informatics (TII), vol. 16, no. 12, pp. 7556-7565, December 2020. (JCR Q1, IF 10.2)
5. H. Wang, X. Guo*, S. Tan, C. Zhang, H. Tang, and Y. Yuan, "Leakage-aware predictive thermal management for multi-core systems using echo state network", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 7, pp. 1400-1413, July 2020. (CCF A rank)
6. H. Wang, T. Xiao*, D. Huang*, L. Zhang*, C. Zhang, H. Tang, and Y. Yuan, "Runtime stress estimation for three-dimensional IC reliability management using artificial neural network", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 24, no. 6, pp. 69:1-69:29, November 2019. (CCF B rank)
7. H. Wang, D. Huang*, R. Liu, C. Zhang, H. Tang, and Y. Yuan, "STREAM: Stress and thermal aware reliability management for 3-D ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 11, pp. 2058-2071, November 2019. (CCF A rank)
8. H. Wang, D. Tang*, M. Zhang*, S. Tan, C. Zhang, H. Tang, and Y. Yuan, "GDP: A greedy based dynamic power budgeting method for multi/many-core systems in dark silicon", IEEE Transactions on Computers (TC), vol. 68, no. 4, pp. 526-541, April 2019. (CCF A rank)
9. X. Guo*, H. Wang (corresponding author), C. Zhang, H. Tang, and Y Yuan, "Leakage-aware thermal management for multi-core systems using piecewise linear model based predictive control", Asia and South Pacific Design Automation Conference (ASP-DAC), January 2019, Tokyo, Japan. (Best Paper Award nomination) (CCF C rank)
10. H. Wang, J. Wan*, S. Tan, C. Zhang, H. Tang, K. Huang, and Z. Zhang, "A fast leakage-aware full-chip transient thermal estimation method", IEEE Transactions on Computers (TC), vol. 67, no.5, pp. 617-630, May 2018. (CCF A rank)
11. H. Wang, J. Ma*, S. Tan, C. Zhang, H. Tang, K. Huang, and Z. Zhang, "Hierarchical dynamic thermal management method for high-performance many-core microprocessors", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 22, no.1, pp.1:1-1:21, July 2016. (CCF B rank)
12. L. Zhang*, H. Wang (corresponding author), and S. Tan, "Fast stress analysis for runtime reliability enhancement of 3D IC using artificial neural network", Proc. International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2016.
13. H. Wang, M. Zhang*, S. Tan, C. Zhang, Y. Yuan, K. Huang, and Z. Zhang, "New power budgeting and thermal management scheme for multi-core systems in dark silicon", Proc. IEEE Internation System-on-Chip Conference (SOCC), Seattle, WA, September 2016.
14. W. Liu*, H. Wang, H. Zhao, S. Wang, H. Chen, Y. Fu, J. Ma*, X. Li, and S. Tan, "Thermal modeling for energy-efficient smart building with advanced overfitting technique", Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, January 2016. (invited) (CCF C rank)

Open Source Software

1. Greedy Dynamic Power (GDP)

• The unintegrated GDP code. You can integrate it into a performance-thermal simulator or into your own performance-thermal simulation flow.
• A ready-to-run implementation of integrating GDP into the HotSniper simulator. By running this program, one can readily analyze the performance/power/thermal behavior of a multi/many-core system running multi-threaded benchmarks like the PARSEC benchmark, with optimized active core distributions and power budgets provided by GDP dynamically at runtime.
• Related publication: H. Wang, D. Tang, M. Zhang, S. Tan, C. Zhang, H. Tang, and Y. Yuan, "GDP: A greedy based dynamic power budgeting method for multi/many-core systems in dark silicon", IEEE Transactions on Computers (TC), vol. 68, no. 4, pp. 526-541, April 2019.

Selected Projects

1. Power budgeting and runtime performance optimization of multi-core systems in dark silicon, funded by National Natural Science Fundation of China (NSFC), 2020-2023.
2. Fast analysis and runtime optimization for thermal induced reliability of 3D ICs, funded by National Natural Science Fundation of China (NSFC), 2015-2017.